FSGEN=DISABLED, ORDER=LEFT_RIGHT, FILLSEL=ZEROS, FSSRCSEL=FSIN_EXT, JSEL=LEFT, FSSEN=DISABLED, TXEN=DISABLED, FSINVEN=DISABLED, DDIS=INACTIVE, MBSEL=8BITS, SCLKINVEN=DISABLED
Transmit Control
| FSGEN | DFS Generator Enable. 0 (DISABLED): Disable the internal DFS generator. 1 (ENABLED): Enable the internal DFS generator. |
| FSSEN | DFS Synchronize Enable. 0 (DISABLED): The internal DFS generator starts immediately when FSGEN is set to 1. 1 (ENABLED): Synchronize the rising edge of the internally generated WS signal from the DFS generator to the rising edge of the external WS input signal. |
| DDIS | Transmit Delay Disable. 0 (INACTIVE): The first data bit is sent on the second or later rising edge of SCK after WS changes. 1 (ACTIVE): The first data bit is sent on the first rising edge of SCK after WS changes. |
| FSDEL | Transmit Initial Phase Delay. |
| FSSRCSEL | Transmit Frame Sync Source Select. 0 (FSIN_EXT): The word select or frame sync is input from the WS pin. 1 (FSIN_INT): The word select or frame sync is input from the internal DFS generator. |
| FILLSEL | Transmit Data Fill Select. 0 (ZEROS): Send zeros during unused bit cycles. 1 (ONES): Send ones during unused bit cycles. 2 (SIGN): Send the sign bit of the current sample (MSB-first format) or last sample (LSB-first format) during unused bit cycles. 3 (RANDOM): Send pseudo-random data generated by an 8-bit LFSR during unused bit cycles. |
| JSEL | Transmit Data Justification Select. 0 (LEFT): Use left-justified or I2S-style formats. 1 (RIGHT): Use right-justified format. |
| FSINVEN | Transmit WS Inversion Enable. 0 (DISABLED): Don’t invert the WS signal. Use this setting for I2S format. 1 (ENABLED): Invert the WS signal. |
| SCLKINVEN | Transmit SCK Inversion Enable. 0 (DISABLED): Do not invert the transmitter bit clock. 1 (ENABLED): Invert the transmitter bit clock. |
| ORDER | Transmit Order. 0 (LEFT_RIGHT): Left sample transmitted first, right sample transmitted second. Use this setting for I2S format. 1 (RIGHT_LEFT): Right sample transmitted first, left sample transmitted second. |
| MBSEL | Transmit Mono Bit-Width Select. 0 (8BITS): 8 bits are sent per mono sample. 1 (9BITS): 9 bits are sent per mono sample. 2 (16BITS): 16 bits are sent per mono sample. 3 (24BITS): 24 bits are sent per mono sample. 4 (32BITS): 32 bits are sent per mono sample. |
| TXEN | Transmitter Enable. 0 (DISABLED): Disable the I2S transmitter. 1 (ENABLED): Enable the I2S transmitter. |